1. Field of the Invention
The present invention relates to a synchronous circuit controller, and, more particularly, to a synchronous circuit controller for controlling data transmission between a plurality of synchronous circuits each of which operates at an independent clock.
2. Description of the Prior Art
Conventionally, data transmission has been extensively used between microcomputers which are synchronous circuits operating at independent clock, or between a microcomputer and another device.
In such case, all digital circuits in a synchronous circuit or a first synchronous circuit operate in synchronization with a clock of first phase of the synchronous circuit or a first clock. In addition, all digital circuits in another or a second synchronous circuit operates in synchronization with a second clock in the second phase of the synchronous circuit which differs from the first phase.
In performing synchronous serial communication for transmitting data from the first synchronous circuit to the second synchronous circuit, the first synchronous circuit outputs a first signal in synchronization with the first clock. The second synchronous circuit is necessary to normally operate when it receives the first signal.
Referring to FIG. 7 which shows in a block diagram a communication apparatus using a first synchronous circuit controller for conventional and typical synchronous serial communication to solve the problem, which is described, for example, in Japanese Patent Application Laid-Open No. 8-330932, the communication apparatus using such conventional first synchronous controller comprises a synchronous circuit 1 such as a microcomputer for transmitting data DT in synchronization with a clock CK1, a synchronous circuit 2 such as a microcomputer for receiving data DR in synchronization with a clock CK2, and a delay circuit 101 as a synchronous circuit controller for providing determined delay time for the transmitted data DT, and generating the received data DR.
The synchronous circuit 2 comprises a latch circuit FF21 consisting of a flip-flop for latching the data DR in synchronization with the clock CK2.
Now, the conventional synchronous circuit controller is described for its operation by referring to FIG. 7 and FIG. 8 showing the data transmission operation in a time chart. First, when the synchronous circuit 2 receives data DT transmitted from the synchronous circuit 1 as received data DR, it is necessary to receive it as normal data. In a case where the clocks CK1 and CK2 have the same frequency, and phase difference between them is previously known, desired received data DR is generated by inserting a delay circuit 101 with delay time corresponding the phase difference into the transmission line to delay the transmitted data DT by such delay time. The latch circuit FF21 of the synchronous circuit 2 latches the data DR in synchronous with the clock CK2, thereby being able to normally receive timing of the data DR without entering into a latch disable range of the latch circuit FF21, 1 or the area close to the shaded leading edge of the clock CK2.
However, there is a case where the phase difference between the clocks CK1 and CK2 is not known previously. The first synchronous communication apparatus cannot cope with such case.
As measures against such circumstances, a second conventional synchronous circuit controller is described in Japanese Patent Application Laid-Open No. 7-264175. Referring to FIG. 9 showing the second conventional synchronous circuit controller in a diagram in which components common to those in FIG. 7 designated by the same references, the second conventional synchronous circuit controller comprises a sampling input circuit 201 for delaying output data DT from a synchronous circuit 1 in synchronization with a clock CK1 by a predetermined amount of delay and outputting delay data D1, D2, . . . , DN, in place of the delay circuit 101, a latch circuit 202 for latching the delay data D1, D2, . . . , DN in synchronization with a clock CK2, and outputting latch data L1, . . . , LN, a transient point detector circuit 203 consisting of an EXOR circuit etc., which EXOR circuit detects two transient points where phases of the latch data L1, . . . , LN are inverted, and outputs transient point detection signals T1, . . . , TN, a transient point output circuit 204 for sequentially encoding the transient point detection signals T1, . . . , TN in one direction from MSB, and outputting transient points A and B in this direction, a select signal generator circuit 205 for detecting a phase substantially at the center between the transient points A and B, and outputting a corresponding select signal PC, and a select circuit 206 for selecting one of the delay data D1, D2, . . . , DN as synchronous data DR in response to control by the select signal PC.
Now, the operation is described for the second conventional synchronous circuit controller with reference to FIG. 9. The sampling input circuit 201 delays the data DT supplied from the synchronous circuit 1 and in synchronization with the clock CK1 in a predetermined interval, and outputs delay data D1, D2, . . . , DN. The latch circuit 202 latches each of the delay data D1, D2, . . . , DN in synchronization with the clock CK2, and supplies the latch data L1, . . . , LN to the transient point detector circuit 203. The transient point detector circuit 203 detects two amplitude transient points or phase inverting points from 1 to 0 or 0 to 1 of latch data L1, . . . , LN, and outputs transient point detection signals T1, . . . , TN. The transient point output circuit 204 sequentially encodes the supplied transient point detection signals T1, . . . , TN in a direction from MSB to LSB, outputs transient points A and B at the MSB side, and supplies them to the select signal generator circuit 205. The select signal generator circuit 205 detects a phase substantially at the center between the transient points A and B, and supplies a corresponding select signal PC to the select circuit 206. The select circuit 206 selects one of delay data D1, D2, . . . , DN corresponding to the select signal PC, for example, D4, as synchronous data DR, and supplies it to the synchronous circuit 2.
In other words, it detects two phase inverting points representing one-bit width of data DT, detects a phase substantially at the center between these phase inverting points, and outputs delay data corresponding to the phase as synchronous data DR.
This enables it to accurately transmit and receive data even when the phase is not known previously.
Since the first conventional synchronous circuit controller corrects the phase difference using the delay circuit which has a fixed delay time corresponding to the previously known phase difference between the first and second synchronous circuits, it has a disadvantage that it cannot be applied to a case where the phase difference is unknown.
In addition, the second conventional synchronous circuit controller which is intended to solve the above problem detects phase inverting points at respective two points of a plurality of delay data as phase correction candidates, selects a suitable pair from them as data subject to phase correction, determines the center between the data subject to phase correction as a select signal, and selects one of the plurality of delay data as the phase difference correction data with the select signal. Therefore, there is a disadvantage that the circuit is increased for its scale because of such processing.
In addition, the second conventional synchronous circuit controller has a disadvantage that it is exclusive for serial data, and cannot be applied to synchronous control for parallel data.
An object of the present invention is to provide a synchronous circuit controller which attains accurate parallel data transmission between a plurality of synchronous circuits operating in synchronization with independent clocks, and suppresses increase of the circuit scale to the minimum.
According to a first aspect of the present invention, a synchronous circuit controller transmits a first N-bit (N being an integer) parallel data signal output in synchronization with a first clock in a first phase to a second synchronous circuit latching the first signal in synchronization with a second clock in a second phase independent from the first clock by adjusting phase difference between the first and second phases, and outputting it as a second data signal in synchronization with the second clock, the controller comprising:
a delay section for delaying the first data signal by M times (M being an integer) in a step of predetermined amount of delay, and outputting corresponding first to M-th delay data;
a latch section for latching each of the first data signal and first to M-th delay data in synchronization with the second clock, and outputting a data latch signal and first to M-th delay latch signals;
a comparator circuit for comparing the data latch signal and the first to M-th delay latch signals each other in the ascending order of the amount of delay, detecting matching or non-matching between signals to be compared, and outputting first to M-th comparison signals corresponding to respective comparison results; and
a selector circuit for selecting one of the data latch signal and the first to (M-1)-th delay latch signals in response to control of the first to M-th comparison signals as the second data signal.
According to a second aspect of the present invention, a synchronous circuit controller transmits a first N-bit (N being an integer) parallel data signal output in synchronization with a first clock in a first phase to a second synchronous circuit latching the first signal in synchronization with a second clock in a second phase independent from the first clock by adjusting phase difference between the first and second phases, and generating and outputting the second clock, the controller comprising:
a delay section for delaying a third clock corresponding to the second clock by M times (M being an integer) in a step of predetermined amount of delay, and outputting corresponding first to M-th delay clocks;
a latch section for latching the first data signal in synchronization with the third clock and the first to M-th delay clocks, and outputting a data latch signal and first to M-th delay latch signals;
a comparator circuit for comparing the data latch signal and the first to M-th delay latch signals each other in the ascending order of the amount of delay, detecting matching or non-matching between signals to be compared, and outputting first to M-th comparison signals corresponding to respective comparison results; and
a selector circuit for selecting one of the third clock and the first to M-th delay clocks in response to control of the first to M-th comparison signals as the second clock.